ASE Expands PowerSiP™ Platform for Next-Generation AI Power Delivery

Dr. Harrison Chang, Vice President of Corporate Research and Development at ASE

“Power efficiency is becoming a defining challenge for next-generation AI systems”

Dr. Harrison Chang, Vice President of Corporate Research and Development at ASE

“By shortening the high-current transmission path, our vertically integrated PowerSiP™ solution can reduce parasitic routing losses by 50% or more, translating directly into meaningful power savings at the system level.”

Dr. C. P. Hung, Vice President of Corporate Research and Development at ASE

“AI systems are placing unprecedented demands on board-to-chip power delivery, making the final stage of voltage regulation increasingly important”

Dr. C. P. Hung, Vice President of Corporate Research and Development at ASE

“PowerSiP™ brings together advanced packaging and integration technologies that enable compact, high-density voltage regulation to be positioned directly beneath the processor, addressing the stringent space and performance requirements of next-generation AI systems.”

Yin Chang, Executive Vice President at ASE

“As AI infrastructure evolves toward increasingly heterogeneous and modular compute architectures, system-level power efficiency will become even more critical.”

Yin Chang, Executive Vice President at ASE

“The expansion of PowerSiP™ reflects ASE’s focus on packaging innovation that addresses broader system-level power challenges”

Yin Chang, Executive Vice President at ASE

“Our qualified assembly technologies provide customers with a flexible toolbox for building compact, highly integrated VRMs that can be vertically integrated for next-generation GPUs, TPUs and custom ASICs in AI data center and HPC applications.”